1. Field of the Invention
The present invention generally relates to the design and fabrication of register file cells implemented in integrated circuits (ICs) and, more particularly, to small multi-port register file cells that are very fast and suitable for very large scale integration (VLSI).
2. Description of the Prior Art
High performance in register files is hindered by the bit line loading presented by multiple ports. High performance via known conventional means implies large cell sizes, or complex and tightly controlled sense amplifier timing. Register files contained in VLSI circuit chips are inaccessible for stand-alone testing, and are not conventionally testable as logic via level-sensitive scan design (LSSD) circuitry. Typically, some additional circuitry is required. Such circuitry implies an overhead to the area, the performance, and the design of the register file.
In order to achieve small cells for multi-port register files it is advantageous to implement both single-ended reading and writing. A conventional register file cell is shown in FIG. 1, for a case of two write ports and four read ports. The storage element of the cell is composed of a cross-coupled-inverter pair 11 and 12 connected between the write pass gates 13 and 14 and a third inverter 15. The output of the third inverter 15 is connected to the four read pass gates 16, 17, 18, and 19, each of which is coupled to a respective bit line. The multiple bit lines and their associated pass gates 16 to 19 present significant loading to the cross-coupled-inverter storage element 11 and 12, hence typically a third, larger, inverter 15 and large read pass gates are required to drive the read bit lines.
Typically, in microprocessors, the single-ended bit lines drive static inverters, and the read word lines are static. In such case, when a read address changes a new read pass gate conducts and, in the case of opposite data, requires the bit line and output inverter to switch to the opposite state. As processor performance increases, it becomes increasingly difficult to design dense cells for rapidly driving the multi-port loading.
Another approach to the high-performance problem is to employ dual-rail bit lines, i.e., a bit line and its complement, and employ differential sense amplifiers, such as used in static random access memories (SRAMs) and dynamic random access memories (DRAMs). Disadvantages of this approach are the doubling of the number of bit lines, and the added complications of precharging bit lines and timing the precharge and setting of the sense amplifiers.
U.S. Pat. No. 4,852,061 to Baron et al. discloses a high density, high performance register file that uses a single, unique bit line for each cell in a column and wherein all read bit lines control devices in a multiplexer. However, Baron et al. make no mention of multi-port read and write applications. Furthermore, the Baron et al. register file is organized into a single array, and writing is done via complementary write bit lines; i.e., there are two separate write bit lines for a single write port. Implementing a large multi-port register file by simply expanding upon the teaching of Baron et al. would result in many more read bit lines and write bit lines than desirable. For example, a 3-write port, 3-read port, 32 register file would require 32 read bit lines and six write bit lines per dataflow bit following the Baron et al. approach. This number of lines is a significant disadvantage to the Baron et al. design. In general, the fewer number of lines, the more dense the array, and hence the more suitable the file to a VLSI environment. In addition, the test circuitry implemented by Baron et al. does not allow a full knowledge of the contents of every cell after multi-port read and writes in any single test cycle.